CVE-2026-23554
Use after free of paging structures in EPT
7.8CVSSHIGH
Description
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
CVSS Vector Breakdown
Exploitability
AV:LAttack VectorLocal
AC:HAttack ComplexityHigh
PR:LPrivileges RequiredLow
UI:NUser InteractionNone
Scope
S:CScopeChanged
Impact
C:HConfidentialityHigh
I:HIntegrityHigh
A:HAvailabilityHigh
Weaknesses
Affected Products
Attack Graph
Products CVE Techniques Tactics
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Exploitability
Official Patch Available
Workaround Available
MITRE ATT&CK
1 technique Privilege Escalation
References
Timeline
Published
Mar 23, 2026
Last Updated
Apr 10, 2026
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