Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
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CVSS Vector Breakdown
Exploitability
AV:LAttack VectorLocal
AC:LAttack ComplexityLow
PR:HPrivileges RequiredHigh
UI:NUser InteractionNone
Scope
S:CScopeChanged
Impact
C:HConfidentialityHigh
I:HIntegrityHigh
A:NAvailabilityNone
Weaknesses
Affected Products
and 17 more affected products View all →
Exploitability
Official Patch Available
References
Timeline
Published
Jan 14, 2026
Last Updated
Jan 26, 2026
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